Flip Flops (1 Viewer)

[hys]

can someone explain a FLIP FLOP works

i try to a truth table for the NAND flip flop

but i didnt get the right results

 

[sunny]

Do you know some electronics?

If so...you can draw out a schematic for the NAND gate flip flop and logically work it out.

There are also many types of flip flops: RS, D, T, and JK

 

[hys]

Yeah, i've been looking at the schematic diagrams

and truth tables and i've been tracing the data

but i can't get it to match can someone send some resources


i'm reading from page 364 and 365 of the PEC Samuel Davis SDD book.

 

[fatmuscle]

if I can scam the UTS java thing, I will

it's a great learning too for Logic gates

 

[hys]

wot UTS java thing

 

[SamD]

The operation of flip-flops (or more correctly, the latch or storage or feedback part of the flip-flop) is difficult to explain fully in a textbook. An interactive demo is what's really needed, a good one, with good explanations can be found at

http://www.play-hookey.com/digital/rs_nand_latch.html

Hope this helps.

Sam

 

[gandalf]

Flip flops will make more sense if you actually build one.

This link has a java applet which allows you to build circuit diagrams online. you can then "run" them to see what happens.

When you build your flip flop, you should find that when the power is initially off, there will be no "light" on the output side. When you apply power the light will go on. Miraculously, when you "switch off the power", the light will "stay on" .. ie, if the "light" represents a bit, we have stored a "bit" of information. Therefore, the flip flop is the basis for all of the RAM inside the computer you are using now ... pretty cool.

The site also has simulations of all of the searches and sorts in the syllabus, as well as heaps of other really interesting stuff.

 

[hys]

from page 364 and 365 of the PEC Samuel Davis SDD book.

does the positions of S or R matter... ( that is either top left or right)

 

[gandalf]

ummm ... errr .... I dont have that book, so I can't tell from here ... perhaps if you hold it up to the screen .... *smiles*

 

[hys]

Sorry this is the RS NAND layout they used in the book..

and i just used that layout to draw those pictures...

i will post RS NOR on following post

 

[hys]

Sorry this is the RS NOR layout they used in the book..

and i just used that layout to draw those pictures...

 

[gandalf]

Well, I could tell you the answer, but why dont you put the diagram into the java applet whose link I gave you above and find out for your self.


;-)



(Doesn't that just sound like a teacher ?!?!)

 

[hys]

yeah it works. depending on how you look at it...

but does it matter which way u do in the HSC

 

[SamD]

The important thing to remember is that the resting state of the RS NOR latch is when both inputs are zero. This is the way the latch is for most of its life. It is only when you wish to alter the bit stored that a pulse (one) is applied to the appropriate input. If voltage is applied to the Set (S) input then the latch stores a 1, which is read or output at Q. If voltage (one) is applied to the Reset (R) input then the latch will store a zero (read at Q). The latch continues to store its value for as long as both inputs remain as zeros. Simultaneous inputs of 1 at both S and R are not allowed as this results in unpredictable behaviour.

An RS NAND latch behaves in a similar way but the inputs need to be reversed to achieve the same results. This is why the inputs for an RS NAND latch are labelled as S bar and R bar rather than just S and R.

If you're using my book the details of how the 1 is clocked into the latch reliably and also how the illegal 1 1 input is avoided are explained on pages 365 and 366.

Let me know if you have any more questions.

Hope this helps,

Sam