Fetch-Execute cycle (1 Viewer)

[SadCeliac]

Hey all,

Is this right??

The fetch-execute cycle involves the performance of an instruction by the CPU, taking it from memory and splitting it into it's opcode and operand to calculate a result and change memory.

1) Program counter (which stores the current location of the instruction being run) is accessed
2) Via registers and data buses, the instruction at the location in memory (provided by the PC) is accessed
3) The instruction is split into opcode and operand (stored in a seperate register)
4) the ALU performs the requested instruction and stores the result in the accumulator (used as temporary storage)
5) PC increments and the next instruction is performed

Thanksss,

 

[SadCeliac]

putting this here for yall because why not

 

[carrotsss]

man I wish my school offered SDD

 

[SadCeliac]

man I wish my school offered SDD

technically I do it through another school on an online course, but yeah, it's quite fun

 

[constexpr]

You've missed a few important components of the fetch execute cycle including the MDR (memory data register) and MAR (memory address register). You've also missed one of the core components being the control unit.

The ALU unit does not always perform the instruction, it is the responsibility of the control unit to decode the opcodes and if required, send data to the ALU for arithmetic. In the case of this assembly instruction: mov eax, 5 the ALU isn't required as there are no arithmetic operations here to be taken place, hope this helps

 

[carrotsss]

I personally like this video more: Tom Scott chokes on vape - YouTube

why'd u delete all of ur messages

 

[carrotsss]

I tried to get off bos... but obviously it didn't work -_-

that’s valid we’ve all been there

 

[SadCeliac]

Hey all,

Is this right??

The fetch-execute cycle involves the performance of an instruction by the CPU, taking it from memory and splitting it into it's opcode and operand to calculate a result and change memory.

1) Program counter (which stores the current location of the instruction being run) is accessed
2) Via registers and data buses, the instruction at the location in memory (provided by the PC) is accessed
3) The instruction is split into opcode and operand (stored in a seperate register)
4) the ALU performs the requested instruction and stores the result in the accumulator (used as temporary storage)
5) PC increments and the next instruction is performed

Thanksss,

bump - summarising again to confirm

1) Program counter (which stores the current location of the instruction being run) is accessed
2) Via registers and data buses (specifically MDR and MAR), the instruction at the location in memory (provided by the PC) is accessed
3) The instruction is split into opcode and operand and stored in the CIR
4) the ALU performs the requested instruction and stores the result in the accumulator (used as temporary storage)
5) PC increments and the next instruction is performed